Principles of Verifiable RTL Design

The goal of the second edition is to keep the topic current. Principles of Verifiable RTL Design, Second Edition tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.

To support more effective use of the Second Edition by its readers, this web site includes the

• Instant Reference free, printable pdf file listing Verifiable RTL language elements for logic designers and students.

• bibliography, with active links to referenced material available on the web,

• examples that users can copy to their computers and study with verification software (simulators, formal tools, etc). and

• script that users and lint tool vendors can download and apply to checking a lint tool's ability to measure Verilog text for its adherence to the Principles of Verifiable RTL Design.