Advanced Debugging/Editing/Planning Tool

[ Documentation | Screenshots | Download | Design Notes | Feature Request | Bug Log | Tutorial

Advanced Debugging/Editing/Planning Tool (ADEPT) is a free tool that helps users with Xilinx FPGA designs including pin editing, design planning/review, documentation, debugging, etc. Please join ADEPT User Group if you would like to receive ADEPT announcements and updates. 

Documentation

Screenshots/Example Spreadsheets

 Download

This page is updated frequently. Please click "Refresh" button on your web browser if any link appears missing  because your browser may use a cached version of the old page.
IMPORTANT: 
If files below have been customized, please back them up before installing the new version on top of the old version:
  • $ADEPT_INST_DIR\lib\gt11_attrs.csv
  • $ADEPT_INST_DIR\lib\gt11_pins.csv
  • $ADEPT_INST_DIR\lib\gtp_attrs.csv
  • $ADEPT_INST_DIR\lib\gtp_pins.csv
Linux version is available upon request.
Nov  20, 09: ADEPT 0.38.6 is the latest version.   7zip compressed (4.4MB)       Winzip compressed (5.3MB)
Updates:
  • Added View->DSP48 View for Virtex5
  • Enhancements to Tools->Special Pin Setup function
  • "File->Generate ViewDraw Symbol" function now supports Virtex6
  • "MGT Pin View" and "Show MGT Map in Excel" now support Virtex6 HXT devices
  • "File->Generate ViewDraw Symbol" function now supports Spartan6
  • Virtex4 support dropped
  • Fixed bug #72, #73, #74, #75

Sep 16, 09: ADEPT 0.38.0 is released. 
Updates:
  • ISE 11.3 is supported.
  • Added "Configuration Setup" function for Virtex6
  • "Show MGT Map in Excel" now supports Spartan6.
  • "Show Table in Excel" now supports Spartan6.
  • Component View and Logic Utilization View now support Spartan6
  • Added "Make Part Compatible" function for Spartan6
  • "MGT Pin View" now supports Spartan6
  • Added initial support for Sparta6
  • Added support for Virtex6
  • Added DRC for Spartan3ADSP
  • Fixed bug #65, #66, #67, #68, #69, #70
May 12, 09: ADEPT 0.37.0 is released.
Updates:
  • ISE 11.1 is supported.
  • Add "Expand/Collapse All" on Logic Utilization View
  • PULLUP/PULLDOWN from UCF/CSV are now supported.
  • Export "Diff_Term" column when export table to Excel
  • Show placed signal names in footprint Excel spreadsheet.
  • Added "View->IO Bank View"
  • Added DRC for DCI_CASCADE
  • Export "Prohibit" column when export table to Excel
  • Pinout CSV file exported is now compatible with PlanAhead
  • Export to Top Level HDL supports VHDL
  • Fixed bug #057, #058, #059, #60, #61, #63, #63, #64
Click to see release notes for all versions

Design Notes

Generate Orcad Symbol

Feature Request

Please email the author if you want to have new features added.

Click to see the complete feature request

Bug Log

Please report any bug to the author.
Click to see the complete bug log

Tutorial

A tutorial document and test NCD/UCF files are included in adept_tutorial.zip.

Go to Jim Wu's Tool Page


Please contact (jimwu88 NOOOSPAM at yahoo NOOOSPAM dot com) if you have any question or comment.