Advanced Debugging/Editing/Planning Tool

User Guide

Author: Jim Wu (jimwu88 at yahoo dot com)

http://mysite.verizon.net/jimwu88/adept/

THIS SOFTWARE IS A FREEWARE. THIS SOFTWARE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION.

THIS SOFTWARE IS PROVIDED "AS IS" AND WITHOUT ANY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY O LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Table of Contents

1.5. Initialization File. 8

2.1.3. Read CSV File. 9

2.1.4. Read NCD File. 10

2.1.5. Read Map Report 10

2.1.6. Export PIN LOC to UCF. 10

2.1.7. Export INST LOC to UCF. 11

2.1.8. Export Pinout to CSV File. 11

2.1.9. Export CSV for Orcad Symbol 11

2.1.10. Export to Top Level HDL. 11

2.1.11. Load Project 11

2.1.12. Save Project 11

2.1.13. Save History to File. 11

2.1.14. Exit 12

2.2. Edit 13

2.2.1. Swap Signal Banks. 13

2.2.2. Edit IO Data…... 13

2.2.3. Select/Clear/Cut/Paste Rows. 13

2.2.4. Preference…... 13

2.3. View.. 14

2.3.1. Pin Table View.. 14

2.3.2. Component View.. 15

2.3.3. Clock Region View.. 16

2.3.4. MGT Pin View.. 17

2.3.5. MGT Attribute View.. 18

2.3.6. MGT Connection View.. 19

2.3.7. Logic Utilization View.. 20

2.3.8. Control Set View.. 21

2.3.9. IO Bank View.. 21

2.3.10. Show Pin Table Stats. 22

2.3.11. Display IDELAYCTRL. 23

2.3.12. Display BUFIO/BUFR.. 23

2.3.13. Display MGT. 23

2.3.14. Display Pad Name. 23

2.3.15. Display Trace Length. 23

2.3.16. Display IO Attributes. 24

2.3.17. View in FPGA_EDITOR.. 24

2.4. Options. 25

2.4.1. Prohibit VREF Pins. 25

2.4.2. Prohibit VRP/VRN Pins. 25

2.4.3. Prohibit Configuration Pins. 25

2.4.4. Include Unused IO in CSV.. 25

2.4.5. Generate PROHIBIT in UCF. 25

2.4.6. Generate Pin LOC on One Line in UCF. 25

2.4.7. Generate IOSTANDARD/DRIVE/SLEW in UCF. 26

2.4.8. Generate Clock Component LOCs and Area Groups in UCF. 26

2.4.9. Generate DSP LOCs in UCF. 26

2.4.10. Generate RAMB LOCs in UCF. 26

2.4.11. Generate RPM LOCs in UCF. 26

2.4.12. Show MGT Power Pins in Excel 27

2.4.13. Append CR XmYn to IO in Excel 27

2.4.14. Show All Pins in Excel Table. 27

2.4.15. Append Bank # to IO in FED.. 27

2.5. Tools. 28

2.5.1. Run DRC.. 28

2.5.2. Generate FPGA Editor Script 28

2.5.3. Port Pinout 28

2.5.4. Make Part Compatible. 28

2.5.5. Configuration Setup. 29

2.5.6. Update SLICE_XY in UCF. 30

2.5.7. Diff MGT Attributes. 30

2.5.8. Diff MGT Connections. 30

2.6. Excel 31

2.6.1. Show Footprint in Excel 31

2.6.2. Show Pin Table in Excel 31

2.6.3. Show Die in Excel 31

2.6.4. Show MGT in Excel 31

2.6.5. Show Component in Excel 31

2.6.6. Show Clock Region View in Excel 31

2.6.7. Show MGT Attribute in Excel 31

2.6.8. Show MGT Connection in Excel 31

2.6.9. Show Logic Utilization in Excel 31

2.6.10. Show Clock Skew Map in Excel 31

2.6.11. Show Control Set in Excel 31

2.7. Help. 32

2.7.1. ADEPT User Guide. 32

2.7.2. About 32

3. Design Information Entry Window.. 33

3.1. Family. 33

3.2. Device. 33

3.3. Package. 33

4. Command Buttons. 33

5.4. Pin Number Column. 34

5.5. SLCR (Show Local Clock Region) Column. 34

5.6. Signal Name Column. 34

5.7. Bank Column. 34

5.8. Pad Column. 35

5.9. Type Column. 35

5.10. Differential Pair Column. 35

5.11. Prohibit Column. 35

5.12. Slice Reference Column. 36

5.13. Trace Length Column. 36

5.14. IO Attributes Columns. 36

5.15. IODELAY Column. 36

6. History Window.. 37

7. Status Bar 37

8. Appendix A: Port PCI Pinout 37

9. Appendix C: Export CSV for Orcad Symbol 37

Table of Figures

Figure 1 Pin Table View.. 15

Figure 2 Component View Screenshot 16

Figure 3 Clock Region View.. 17

Figure 4 MGT Pin View.. 18

Figure 5 MGT Attribute View.. 19

Figure 6 MGT Connection View.. 20

Figure 7 Logic Utilization View.. 21

Figure 8 Control Set View.. 21

Figure 9 IO Bank View.. 22

Figure 10 Make Part Compatible Window.. 29

Figure 11 Configuration Setup Window.. 29

1. Introduction

1.1. Purpose

Advanced Debugging/Editing/Planning Tool (ADEPT) is developed to help users on FGPA implementation including pin editing, design planning/review, documentation, debugging, etc.

1.2. Features

The main features of the tool are listed below:

· Interactive regional clock display

· Easy of use pinout editing/manipulation

· Component view with instance names extracted from NCD

· Clock region view of global clock routing resource usage

· Tabulated MGT attribute view with diff function

· Tabulated MGT connection view with diff function

· Support various file formats (UCF, CSV, Excel spreadsheets) for use in implementation tools as well as for documentation generation

1.3. Install

IMPORTANT:

If files below have been customized, please back them up before installing the new version on top of the old version:

$ADEPT_INST_DIR\lib\gt11_attrs.csv
$ADEPT_INST_DIR\lib\gt11_pins.csv
$ADEPT_INST_DIR\lib\gtp_attrs.csv
$ADEPT_INST_DIR\lib\gtp_pins.csv

ADEPT requires ISE to run. ISE releases listed below are supported. It uses the ISE installation pointed by XILINX and PATH environment variable. The directory for ISE command line tools needs to be included in the PATH environment variable.

· ISE 9.2.04

· ISE 10.1, 10.1.01, 10.1.02, 10.1.03

· ISE 11.1, 11.2

Please follow the steps below to install ADEPT:

1. Unzip adept_NN_MM.zip file to a directory, where NN_MM is the ADEPT version number. Please take a note of the directory name. Make sure the directory structure in the zip file is preserved.

adept

doc : sub-directory

lib : sub-directory

tmp : sub-directory

adept.exe : executable

adept_example.ini : example .ini file

release_note.html : release note

2. Set the environment variable ADEPT_INST_DIR to the directory where adept.exe resides (i.e. unzip_directory\adept). Follow instructions below to set up environment variable on Windows XP:

o Go to desktop

o Right click on "My Computer" and then select “Properties”

o Click "Advanced" tab on the "System Properties" window

o Click "Environment Variables" button at the bottom

o Click "New" button

o Enter ADEPT_INST_DIR as the variable name

o Enter the path (eg: c:\adept) to adept.exe as the variable value

o Click OK on all opened windows

1.4. Uninstall

Please follow the steps below to uninstall the program:

Backup adept.ini and any files that you added/modified in $ADEPT_INST_DIR directory and its sub-directories
Delete $ADEPT_INST_DIR directory
Unset environment variable ADEPT_INST_DIR

1.5. Initialization File

The default values of options used by the tool can be changed with an initialization file adept.ini. The tool searches the file in the following order and will use the first one found:

$HOME\adept.ini

$ADEPT_INST_DIR\adept.ini

An example initialization file $ADEPT_INST_DIR\adept_example.ini is included with the installation. Please rename it to adept.ini before customizing it.

2. Menu Commands

2.1. File Menu

2.1.1. Read UCF

This function reads in a UCF. It clears previous pin placements first before reading the pin assignments in the UCF.

The constraint language does not have a way to specify directions of IO signals in UCF. A “new constraint” DIR is added in ADEPT so that IO directions can be passed to the tool via comments in UCF. Valid values for the DIR constraint are IN, OUT and INOUT. Below are some examples:

NET "data_in<100>" LOC = J26 | IOSTANDARD = LVCMOS25; #DIR = "IN"

NET "data_io<85>" LOC = B32 | IOSTANDARD = LVCMOS25; #DIR = "INOUT"

NET "data_out<30>" LOC = V9 | IOSTANDARD = LVCMOS25; #DIR = "OUT"

2.1.2. Append UCF

This function appends a UCF to the pin table. It keeps previous pin placements and only adds new pin placements from the UCF.

2.1.3. Read CSV File

This function reads a CSV file with IO information.

The installation includes an example CSV file, $ADEPT_INST_DIR\doc\csv_example.csv. The first non-comment line in the CSV file defines the contents in each column. Below is the list of all the columns that the command looks for:

Pin Number

Signal Name

Direction

Prohibit

IO Standard

Drive (mA)

Slew Rate

Diff Term

Driver Group

Driver Type

The “Signal Name” column is required. All other columns are optional. The columns can be in any order.

DCI_CASCADE constraints can also be added to the CSV file using comments like the example below:

# CONFIG DCI_CASCADE = "15 13 21";

This function works with CSV files directly exported from PlanAhead and the pad CSV file generated by PAR.

2.1.4. Read NCD File

This function reads a NCD file for generating Component View, Clock Region View, MGT Attribute View, MGT Connection View and Logic Utilization View. The dialog window will pop up asking what information to extract from the ncd. The default selection can be changed by setting the variables below in adept.ini file:

# 1 = turn on the option

# 0 = turn off the option

# get clock region report from ncd

set ProgramOptions(NcdGetClockRegion) 0

# get instance names from ncd

set ProgramOptions(NcdGetInstNames) 0

# get mgt connections from ncd

set ProgramOptions(NcdGetMgtConnections) 0

# get logic utilization from ncd

set ProgramOptions(NcdGetLogicUtilization) 1

The tool also checks the clocking rules below after the ncd is read in:

Virtex4:

Check if more than 8 global clocks are in a clock region
Check if a clock region is out of reach of BUFIO or BUFR
Check if more than 2 regional clocks are in a clock region

2.1.5. Read Map Report

This function reads .mrp or .map report generated by map:

If .mrp file is selected, the tool reads in the control set information in the detailed map report (map -detail option) and displays the information on “View->Control Set View”.
If .map file is selected, the tool reads in the clock placement information and displays the info on “View->Clock Region View”. This is useful for debugging clock placement issues without a NCD file.

2.1.6. Export PIN LOC to UCF

This function exports “PIN LOC” and optional “IOSTANDARD” constraints for placed pins to UCF. It can also optionally export “CONFIG PROHIBIT” constraints for prohibited pins.

e.g.:

# Pins prohibited in the PROHIBIT column

CONFIG PROHIBIT = "W3";

# pins assigned on bank 5

NET TEST_IN LOC = C17;

2.1.7. Export INST LOC to UCF

This function exports constraints below to UCF depending on selected components and/or signals. The “Get instance names/MGT attributes” option MUST be checked when reading a NCD before the tool can export the instance LOCs to UCF.

INST LOC

INST RLOC_ORIGIN

AREG_GROUP defined with CLOCK_REGIONs

Example:

# INST LOC constraints

INST clk0/dcm_clk0 LOC = BUFGCTRL_X0Y5;

INST clk0/DCM_BASE0 LOC = DCM_ADV_X0Y1;

INST dsp0 LOC = DSP48_X0Y13;

INST ram0 LOC = RAMB16_X0Y20;

#INST RLOC_ORIGIN constraints

INST "my_rpm" RLOC_ORIGIN = SLICE_X30Y68;

# AREA_GROUP constraints

NET "REFCLK200" TNM_NET = "TN_REFCLK200";

TIMEGRP "TN_REFCLK200" AREA_GROUP = "CLKAG_REFCLK200";

AREA_GROUP "CLKAG_REFCLK200" RANGE = CLOCKREGION_X0Y0;

2.1.8. Export Pinout to CSV File

This function exports the current pinout to a CSV file. The exported CSV file can be imported into PlanAhead or read in by ADEPT. The CSV file may also include DCI_CASCADE information when passed from UCF.

2.1.9. Export CSV for Orcad Symbol

This function exports all package pins to a CSV file in the same format that Orcad Capture symbol generation spreadsheet uses. Please see the appendix C for details.

2.1.10.Export to Top Level HDL

This function exports all placed signals to a top level HDL file. If the output file extension is “.vhd”, the output will be exported in VHDL. Otherwise, the output will be in Verilog.

2.1.11.Load Project

This function loads an ADEPT project file.

2.1.12.Save Project

This function saves the current device, UCF and NCD information to an ADEPT project file. The project file can be loaded with “Load Project” function.

2.1.13.Save History to File

This function saves the log in the “History” window to a File.

2.1.14. Exit

This function exits out of the tool.

2.2. Edit

2.2.1. Swap Signal Banks

This Virtex4 only command swaps the signals between banks. A window pops up to allow user to enter the source banks and the destination banks. Comma separated bank numbers are accepted. e.g.

Source Bank: 6,10

Destination Bank: 12,8

The tool will perform 2 swaps in sequence in this case. It first swaps the signals between bank 6 and bank 12. It then swaps the signals between bank 10 and bank 8.

After the swapping is done, the suggested values for X delta, Y delta and “Flip Horizontally” are printed in the “History Window” so they can be used with “Update SLICE_XY in UCF” command.

2.2.2. Edit IO Data…

This function opens a window for users to easily edit IO standard, drive, slew, direction, driver group, and driver type. Rows can be selected for editing with the regular mouse clicks (i.e. click once, click->hold->drag->release, ctrl-click, and shift-click). The IO data for all the selected rows will be updated. “Set” button next to an entry box only updates the information for one column. “Set All” button updates IO data for all six columns.

2.2.3. Select/Clear/Cut/Paste Rows

Select Rows:

This function selects rows with predefined filters for VREF, input only and unbonded pads.

Clear Rows:

This function clears the information in the selected rows

Cut Rows:

This function saves the information in the selected rows. These rows will be cleared after “Paste Rows” command.

Paste Rows:

This function paste the information saved from “Cut Rows” command to the selected rows.

2.2.4. Preference…

This function opens the preference window to change tool options:

Bus Delimiter:

Trace Length Unit:

ps: show length in pico-second. The tool uses 7ps/mm by default.
micron: show length in micron. This is the default setting.

Instance Sort Order: it controls the order that instances are displayed on “Component View” and are exported to UCF

by instance name: sort by instance name
by primitive XmYn: sort by primitive XY coordinate. (e.g. RAM36_X0Y8, RAM36_X0Y7, RAMB36_X1Y10, RAMB36_X1Y6, …)

2.3. View

2.3.1. Pin Table View

This function displays the pin table using the default layout: pin numbers are displayed in the order of the following columns: Bank (ascending), TIOI (ascending), and Pad (descending).

Figure 1 Pin Table View

2.3.2. Component View

This function displays DCM, PMCD, BUFGCTRLs global clock pad (GC_P pins) in the order as they are placed on the die (left->right and then top->bottom).

For Virtex4 and Virtex5 devices, there are two rows highlighted in gray in the middle with the text below:

DO NOT CROSS No dedicated routes between top and bottom comps

This informs users the Virtex4 global clocking rule: the outputs from the top clock components do not have dedicated routes to the bottom clock components and vice versa.

The command can also optionally display BUFIO, BUFR, DSP, RAMB/FIFO16, and RPMs that are used in the NCD.

Instance names, clock outputs, and clock regions for these components are also displayed if a NCD is read in (File->Read NCD File).

Figure 2 Component View Screenshot

2.3.3. Clock Region View

This view displays the clock region map with detailed information about clocking components, clock utilization, etc for each clock region. The clock region XmYn coordinates are displayed in the “CR” column. The number of used and total global clocks in a clock region is also displayed in G:used/total format for each clock region. This view also shows the clocking components (DCM, PLL, BUFG, BUFIO and BUFR) in each clock region. Clock regions with errors are highlighted in red.

Figure 3 Clock Region View

2.3.4. MGT Pin View

This function displays all MGT pins grouped by MGT banks.

Figure 4 MGT Pin View

2.3.5. MGT Attribute View

This function displays attributes of all MGTs used in a design. Users can customize which attributes to display and the display order by modifying appropriate file below:

Virtex4: $ADEPT_INST_DIR/lib/gt11_attrs.csv
Virtex5: $ADEPT_INST_DIR/lib/gtp_attrs.csv

The view also has a user-defined column which can be used for any additional information (e.g. DRP address as shown in the screenshot). Please check the attribute CSV file above for instructions on how to customize the view.

Figure 5 MGT Attribute View

2.3.6. MGT Connection View

This function displays pin connections of all MGTs used in a design. Users can customize which pins to display and the display order by modifying appropriate file below:

Virtex4: $ADEPT_INST_DIR/lib/gt11_pins.csv
Virtex5: $ADEPT_INST_DIR/lib/gtp_pins.csv

The view also has a user-defined column which can be used for any additional information (e.g. pin direction). Please check MGT pin CSV file above for instructions on how to customize the view.

Figure 6 MGT Connection View

2.3.7. Logic Utilization View

This function displays the device logic utilization hierarchically.

Figure 7 Logic Utilization View

2.3.8. Control Set View

This function displays the control set information read in by running “File->Read Map Report” from a detailed map report (.mrp generated with map -detail option).

Figure 8 Control Set View

2.3.9. IO Bank View

This function displays all IO banks as IO columns in the order as they are in FPGA_EDITOR. It also displays VCCO and DCI settings for each bank.

Figure 9 IO Bank View

Depending on the device, there may be 3 or 4 IO columns displayed. The column header indicates the IO column an IO bank is in:

OL = Outer Left

CL = Center Left

CR = Center Right

OR = Outer Right

2.3.10. Show Pin Table Stats

This function displays pin table statistics in the History window. The stats for the device as well as each bank are printed. One thing to note is the IO count for each IOSTANDARD within a bank. Below is what the stats look like. In the particular example, bank 19 has 3 IOs HSTL_II and 28 IOs in LVCMOS25_12_SLOW.

Pin Table Statistics

Total available user IO count: 896

Total unplaced IO signal count: 0

Total placed IO signal count: 407

Placed IO signal count by IO standard

LVCMOS25_12_SLOW pins : 39

LVPECL_25 pins : 8

SSTL18_I pins : 200

SSTL18_II pins : 160

Placed IO signal count by IO direction

Input pins : 43

Output pins : 204

Inout pins : 160

No dir pins : 0

…

Pin Table Stats by Bank

Bank 19 stats

Total pin count : 40

Used pin count : 31

Prohibit pin count : 0

IO Standards : HSTL_II:3 LVCMOS25_12_SLOW:28

Vref : NR

Vcco : 0

…

End of Pin Table Statistics

2.3.11. Display IDELAYCTRL

This function displays the information on IDELAYCTRL components. The initial setting can be changed with the variable below in adept.ini:

# Display/Hide IDELAYCTRL

# 1 display

# 0 hide

set ProgramOptions(DisplayIdelayCtrl) 0

2.3.12. Display BUFIO/BUFR

This function displays the information on BUFIO/BUFR components. The initial setting can be changed with the variable below in adept.ini:

# Display/Hide BUFIO/BUFR

# 1 display

# 0 hide

set ProgramOptions(DisplayBufioBufr) 0

2.3.13. Display MGT

This function displays the information on MGT components. The initial setting can be changed with the variable below in adept.ini:

# Display/Hide MGT

# 1 display

# 0 hide

set ProgramOptions(DisplayMGT) 0

2.3.14. Display Pad Name

This function displays the pad names (e.g. IOB_X0Y2) for all pins. The initial setting can be changed with the variable below in adept.ini:

# Display/Hide Pad Name (1 = display; 0 = hide)

set ProgramOptions(ShowPadNameColumn) 0

2.3.15. Display Trace Length

This function displays/hides the “Trace Len” column. The initial setting can be changed with the variable below in adept.ini:

# Display/Hide trace length column

# 1 display

# 0 hide

set ProgramOptions(ShowTraceLenColumn) 0

2.3.16. Display IO Attributes

This function displays/hides the IO standard, drive, slew, direction, driver group, and driver type columns. The initial setting can be changed with the variable below in adept.ini:

# Display/Hide IO attribute columns

# 1 display

# 0 hide

set ProgramOptions(ShowIoAttrColumns) 1

2.3.17. View in FPGA_EDITOR

This function opens the current loaded device in FPGA_EDITOR. It also asks whether or not users want to add the placed IOs in ADEPT to FPGA_EDITOR. The “FED” command button can then be used to synchronize the selection in ADEPT with FPAG_EDITOR. This function requires Perl to work. The command is tested with ActivePerl 5.10. ActivePerl is freely available from http://www.activestate.com/.

2.4. Options

2.4.1. Prohibit VREF Pins

If this option is turned on, the tool prohibits VREF pins from pin assignment. The initial setting can be changed with the variable below in adept.ini:

# 1 = Prohibit VREF pins from pin assignment

# 0 = Include VREF pins for pin assignment

set ProgramOptions(ProhibitVrefPins) 1

2.4.2. Prohibit VRP/VRN Pins

If this option is turned on, the tool prohibits VRP/VRN pins from pin assignment. The initial setting can be changed with the variable below in adept.ini:

# 1 = Prohibit VRP/VRN pins from pin assignment

# 0 = Include VRP/VRN pins for pin assignment

set ProgramOptions(ProhibitVrpnPins) 1

2.4.3. Prohibit Configuration Pins

If this option is turned on, the tool prohibits configuration pins from pin assignment. The initial setting can be changed with the variable below in adept.ini:

# 1 = Prohibit configuration pins from pin assignment

# 0 = Include configuration pins for pin assignment

set ProgramOptions(ProhibitConfigPins) 1

2.4.4. Include Unused IO in CSV

If this option is turned on, the tool also exports unused IOs to the CSV file when running “File->Export Pinout to CSV File…” function. The default value for this option can be changed in adept.ini file:

# 1 = Include unused IO in CSV

# 0 = Do not include unused IO in CSV

set ProgramOptions(IncludeUnusedIoInCsv) 1

2.4.5. Generate PROHIBIT in UCF

If this option is turned on, the tool generates “CONFIG PROHIBIT” constraints for the pins that are prohibited in the PROHIBIT column running “File->Export Pin LOC to UCF”. The default value for this option can be changed in adept.ini file:

# 1 = Generate PROHIBIT for prohibited pins in UCF

# 0 = Do not generate PROHIBIT for prohibited pins in UCF

set ProgramOptions(GenProhibitInUcf) 0

2.4.6. Generate Pin LOC on One Line in UCF

If this option is turned on, the tool generates all attributes for one pin on one line when running “File->Export Pin LOC to UCF”. Otherwise, the attributes will be on separate lines. The default value for this option can be changed in adept.ini file:

# 1 = Generate pin loc constraint/iostandard on one line

# 0 = Generate pin loc constraints on separate lines

set ProgramOptions(GenPinLocOnOneLine) 1

Example:

# attributes on one line

NET "test" LOC = C17 | IOSTANDARD = LVCMOS15;

# attributes on separate lines

NET "test" LOC = C17;

NET "test" IOSTANDARD = LVCMOS15;

2.4.7. Generate IOSTANDARD/DRIVE/SLEW in UCF

If this option is turned on, the tool generates IOSTANDARD/DRIVE/SLEW constraints for the placed pins when running “File->Export Pin LOC to UCF” command. The default value for this option can be changed in adept.ini file:

# 1 = Generate IOSTANDARD/SLEW/DRIVE constraints in UCF

# 0 = Do not generate IOSTANDARD/SLEW/DRIVE in UCF

set ProgramOptions(GenIoStandardInUcf) 0

2.4.8. Generate Clock Component LOCs and Area Groups in UCF

If this option is turned on, the tool generates LOC constraints for both global and regional clock components when running “File->Export INST LOC to UCF” command. The default value for this option can be changed in adept.ini file:

# 1 = Generate clock component LOCs and Area Groups in UCF

# 0 = Do not generate

set ProgramOptions(GenClockLocsInUcf) 1

2.4.9. Generate DSP LOCs in UCF

If this option is turned on, the tool generates LOC constraints for DSP instances when running “File->Export INST LOC to UCF” command. The default value for this option can be changed in adept.ini file:

# 1 = Generate INST LOC for DSP in UCF

# 0 = Do not generate

set ProgramOptions(GenDspLocsInUcf) 1

2.4.10. Generate RAMB LOCs in UCF

If this option is on, the tool generates LOC constraints for RAMB instances when running “File->Export INST LOC to UCF” command. The default value for this option can be changed in adept.ini file:

# 1 = Generate INST LOC for RAMB in UCF

# 0 = Do not generate

set ProgramOptions(GenRambLocsInUcf) 1

2.4.11. Generate RPM LOCs in UCF

If this option is on, the tool generates RLOC constraints for RPM instances when running “File->Export INST LOC to UCF” command. The default value for this option can be changed in adept.ini file:

# 1 = Generate INST RLOC for RPM in UCF

# 0 = Do not generate

set ProgramOptions(GenRpmLocsInUcf) 1

2.4.12. Show MGT Power Pins in Excel

If this option is on, MGT power pins are displayed in Excel when running Excel->Show MGT Map in Excel. The default value for this option can be changed in adept.ini file:

# 1 = Show MGT power pins in Excel

# 0 = Do not append

set ProgramOptions(ShowMgtPowerPinsInExcel) 1

2.4.13. Append CR XmYn to IO in Excel

If this option is on, the clock region XmYn coordinate is are automatically appended to the IO names when showing the table view in Excel. The default value for this option can be changed in adept.ini file:

# 1 = Append clock region XnYm to IO name when exporting table to Excel

# 0 = Do not append

set ProgramOptions(AppendCRXYToIOInExcel) 0

2.4.14. Show All Pins in Excel Table

# 1 = Show all pins (MGT, power, configuration, etc)

# 0 = Only show regular user I/O pins

set ProgramOptions(ShowAllPinsInExcelTable) 1

2.4.15. Append Bank # to IO in FED

If this option is on, the bank numbers are automatically appended to the placed IO names when they are added to FED when running the command “View in FPGA_EDITOR”. The default value for this option can be changed in adept.ini file:

# 1: Append bank number to FED

# 0: Do NOT append bank number to FED

set ProgramOptions(AppendBankInFed) 0

2.5. Tools

2.5.1. Run DRC

This function runs the design rule check on the pinout.

IMPORTANT: The current design rules are listed below. New design rules will be added as they are identified.

Virtex4:

- Signals in the same bank must have the same VCCO

- Signals in the same bank must have the same VREF if required

- VREF pin must NOT be used if VREF is required

- VRP/VRN pins must NOT be used if DCI is used in a bank

- LVDS outputs can NOT be placed on low capacitance (LC) pins

- LVDS25_DT must have VCCO=2.5v

Virtex5:

- Signals in the same bank must have the same VCCO

- Signals in the same bank must have the same VREF if required

- VREF pin must NOT be used if VREF is required

- VRP/VRN pins must NOT be used if DCI is used in a bank

Spartan3E:

2.5.2. Generate FPGA Editor Script

This function generates a script that can be played back in FPGA editor to highlight the selected pads in the pin table view. Pads can selected with several pre-defined filters using “Edit->Select Rows” function.

2.5.3. Port Pinout

IMPORTANT NOTE: This function is NOT a pin-compatibility porting function. It matches the bank numbers and keeps the relative positions of signals within a bank.

This function ports an existing pinout to a different device/package. Virtex4 and Virtex5 are supported.

2.5.4. Make Part Compatible

This function checks the pin compatibility between current selected part and a new device in the same package. The tool creates a spreadsheet that lists all pins from both parts side by side and highlights incompatible pins in red. The “PROHIBIT” column for all incompatible pins are set to yes (“Y”). Once the spreadsheet is reviewed, users can write out a UCF file with PROHIBIT constraints added for all incompatible user IOs.

Figure 10 Make Part Compatible Window

2.5.5. Configuration Setup

This function shows only the relevant configuration pins, their values, types and important notes based on the selection configuration mode and data width.

Figure 11 Configuration Setup Window

2.5.6. Update SLICE_XY in UCF

This Virtex4 only command updates the SLICE_XY LOC constraints in a UCF and save the result to a new UCF. The target device MUST be loaded before running This function. A window will pop up for the user to enter the source UCF, the destination UCF, the SLICE_X delta, the SLICE_Y delta, and whether or not to flip the SLICE_X. The formulas below are used to calculate the final SLICE_XY values:

NEW_SLICE_X = FLIP_X(SLICE_X + SLICE_X_DELTA)

NEW_SLICE_Y = SLICE_Y + SLICE_Y_DELTA

The SLICE_X and SLICE_Y are negative or positive integers.

2.5.7. Diff MGT Attributes

The command runs “diff” on all attributes among selected MGTs. It pops up a window for selecting which MGTs to run “diff” on. The “Row” column for rows with differences is marked in “red”. The source MGT is marked in “green”. MGTs that are different from the source MGT are marked in “red”.

A command “Show Diff Details” can be run from a popup window with the right mouse click to show full contents in the cells with differences in the selected row.

2.5.8. Diff MGT Connections

The command runs “diff” on all pin connections among selected MGTs. It pops up a window for selecting which MGTs to run “diff” on. The “Row” column for rows with differences is marked in “red”. The source MGT is marked in “green”. MGTs that are different from the source MGT are marked in “red”.

A command “Show Diff Details” can be run from a popup window with the right mouse click to show full contents in the cells with differences in the selected row.

2.6. Excel

2.6.1. Show Footprint in Excel

This function exports the package information to Excel and the displays the footprint of the package in Excel spreadsheet

2.6.2. Show Pin Table in Excel

This function exports the pin table with colorization on banks and clock regions to Excel. It’s available for Virtex4, Virtex5 and Spartan3E.

2.6.3. Show Die in Excel

This function exports the die view of the pin table to Excel. The die view displays pins in left, center and right columns just like they are shown in the FPGA Editor. Banks, clock regions and CC pins are colorized. This function is only available for Virtex4 devices.

2.6.4. Show MGT in Excel

This function exports the mgt layout to Excel. This function is only available for Virtex4 devices.

2.6.5. Show Component in Excel

This function exports “Component View” to an Excel spreadsheet.

2.6.6. Show Clock Region View in Excel

This function exports “Clock Region View” to an Excel spreadsheet.

2.6.7. Show MGT Attribute in Excel

This function exports “MGT Attribute View” to an Excel spreadsheet.

2.6.8. Show MGT Connection in Excel

This function exports “MGT Connection View” to an Excel spreadsheet.

2.6.9. Show Logic Utilization in Excel

This function exports “Logic Utilization View” to Excel. The logic utilization can also be saved to a CSV file by selecting “CSV File” as the file type in the “Save File” dialog.

2.6.10. Show Clock Skew Map in Excel

This function exports the clock skew map to an Excel.

2.6.11. Show Control Set in Excel

This function exports the “Control Set View” to an Excel spreadsheet.

2.7. Help

2.7.1. ADEPT User Guide

This function opens this user guide.

2.7.2. About

This function shows the current ADEPT version.

3. Design Information Entry Window

3.1. Family

The Family list box shows the supported FPGA families: Spartan3, Virtex2 and Virtex2P.

3.2. Device

The Device list box shows all available devices for the selected family.

3.3. Package

The Package list box shows all available packages for the selected family and device.

4. Command Buttons

4.1. Load Device

This function loads and displays the information of the selected device.

4.2. Find

This function finds a match of the keyword in one of the following columns in the pin table:

Pin Mumber

Signal Name

Bank

The match is case-insensitive. Wildcards (? and *) can be used in the keyword. It automatically wraps around when the last row of the table is reached.

4.3. Find All

This function finds all matches of the keyword in one of the following columns in the pin table:

Pin number

Signal Name

Bank

The match is case-insensitive. Wildcards (? and *) can be used in the keyword.

4.4. FED

This function synchronizes the selection in ADEPT with FPGA_EDITOR.

5. Pin Table

5.1. General

All columns can be sorted by clicking on column headers. The sort order toggles between ascending and descending. However, the information and color coding in the “SLCR” column should be ignored when the table is not in the default layout. Click “View->Pin Table View” to restore the default layout.

5.2. Row Column

The Row column shows the row number of the pin table in the default pin table layout. This column can not be edited.

5.3. TIOI Column

The TIOI column shows the IOI tile number with a prefix letter indicating the side of the tile as if the device was viewed from the FPGA editor. This column can not be edited.

T = Top side
R = Right side
B = Bottom side
L = Left side
C = Center column (Virtex4/Virtex5)

5.4. Pin Number Column

The Pin Number column shows the pin numbers of the loaded device. The clock regions that can be reached by a local clock (S3, V2/V2P) or a clock capable (CC) I/O (V4) are highlighted in green in this column.

5.5. SLCR (Show Local Clock Region) Column

The SLCR column indicates weather or not to show the local clock region for the selected pin. The SLCR value (Y or N) can only be changed for a local clock or CC pin as indicated in the Type column. If SLCR is “Y” for a pin and the pin is selected, the clock regions that can be reached by this pin are highlighted in green in the Pin Number column. The selected local clock or CC is highlighted in orange. This column can be edited by clicking on it and the value toggles between “Y” and “N”.

For V4 devices, the SLCR column also displays clock region XmYn coordinates for all clock regions.

5.6. Signal Name Column

The Signal Name column shows the signal name that is assigned to the pin number in the same row. This column can be filled from a UCF file or manually edited.

5.7. Bank Column

The Bank column shows the bank number of a pin. This column can not be edited. Different banks are shown in different colors.

5.8. Pad Column

The Pad column shows the pad number of a pin. The picture below shows how the pad number is assigned if the device was loaded in the FPGA editor. This column can not be edited.

5.9. Type Column

The Type column shows the type of a pin. The table below shows the valid values and their purposes. This column can not be edited.

Value	Purpose
VREF	Voltage reference pins
VRP/VRN	designated VRP or VRN pins for DCI.
CC_P	Virtex4: Clock Capable P pins
GC_P	Virtex4: Global Clock P pins
MGT_I	MGT RX pads
MGT_O	MGT TX pads
MGT_XY	MGT XY coordinates
IP	Input only
GCLK	Global clock
RHCLK	Right half clock
LHCLK	Left half clock
MRBUFIO	BUFIO that can drive IOs in multiple clock regions
SRBUFIO	BUFIO that can only drive IOs in a single clock region

5.10. Differential Pair Column

The Differential Pair column indicates where or not two pins are a differential pair. The values for a differential pair have the same number with either a “P” or “N” suffix. Two pins of the same differential pair are highlighted in the same color (gray or light blue. This column can not be edited.

5.11. Prohibit Column

The Prohibit column indicates whether or not a pin is prohibited from placement or editing. This column can be changed by clicking on it. The value is toggled between “Y” and “N”.

5.12. Slice Reference Column

The Slice Reference column shows the closest slice number to a pin. This column can not be edited.

This column can be turned on or off by setting the following variable in adept.ini file:

# 1 = turn on the column

# 0 = turn off the column

# slice reference column

set ProgramOptions(ShowSliceRefColumn) 1

5.13. Trace Length Column

The Trace Length column shows the length (in ps or micron) of the trace that connects the IOB pad and the package ball. The unit of the trace length can be changed from Edit->Preferences menu. The formula below is used for translation between ps and micron:

length_in_ps = 7 * length_in_micron / 1000

This column can be turned on or off using View->Display Trace Length menu.

5.14. IO Attributes Columns

These columns show IO direction, standard, drive, slew, diff term, driver group, and driver type attributes on a signal. They can be turned on or off using “View->Display IO Attributes”.

5.15. IODELAY Column

This column shows the IODELAY types (FIXED or VARAIBLE) for IOs that use IDELAY (Virtex4) or IODELAY (Virtex5). The IODELAY types are populated after a NCD is loaded with “Get instanace names/MGT attributes” checked.

6. History Window

The History window displays the tool activities and information/warning/error messages.

Information messages are printed in “black”.

Warning messages are printed in “blue”.

Error messages are printed in “red”.

7. Status Bar

The Status Bar shows the current loaded device, UCF, and NCD.

8. Appendix A: Port PCI Pinout

Some of the functions in ADEPT can be very helpful on porting an existing PCI pinout to another device. Please check the design note $ADEPT_INST_DIR\doc\pci_pinout_v4.html for details.

9. Appendix C: Export CSV for Orcad Symbol

ADEPT can export a CSV file that can be directly copied and pasted to Orcad Capture part generation spreadsheet to generate a multi-part symbol for the loaded device. Check the design note $ADEPT_INST_DIR\doc\gen_orcad_symbol.html for details.