#include <odio3.h>
Inheritance diagram for oDI3_TPU:

Public Member Functions | |
| oDI3_TPU (IOLINE pin1, IOLINE pin2, IOLINE pin3) | |
| Constructor on 3 channels on TPU port. | |
| uint8 | value (void) const |
| Return value. | |
Static Public Member Functions | |
| int | TCR1 (void) |
| void | TMCR (int iarb) |
| bool | HSQR (int chan, int val) |
| Configures the host sequence register. | |
| bool | HSRR (int chan, int val) |
| Configures the host sequence request register. | |
| bool | CPR (int chan, int val) |
| Configures the channel priority register (Ref. TPU Channel Utilization). | |
| bool | CIER (int chan, int cie) |
| Configures the channel interrupt enable register. | |
| int | CISR (int chan) |
| Returns the channel interrupt status register. | |
| void | CISR_clear (int chan) |
| Clears the channel interrupt status register for the channel. | |
| bool | TICR (int cirl, int cibv) |
| Configures the TPU interrupt configuration register. | |
| int | tpu_vector (IOLINE channel) |
| Given a channel, returns the vector number to use for an interrupt. | |
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Configures the channel interrupt enable register.
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Configures the channel priority register (Ref. TPU Channel Utilization).
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Configures the host sequence register.
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Configures the host sequence request register.
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misnomer--should be TCR1 divisor--return number of clocks (PSCK,TCR1P modifications) Globally available object. Can be used in combination with TPU_REGISTER definition to say TPU_REGISTER->CFSR.BITS... |
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was tpu_init Configures the channel function select register |
1.3